The semiconductor industry continuously improves the integrated density of various electronic components by sustainably decreasing the minimum characteristic size, such that more electronic components can be integrated under the situation of a given area. At present, the most advanced package solutions include a wafer level chip-scale package, a fan-out wafer level package, a flip chip and a package on package (POP), etc.
The traditional fan-out wafer level package (FOWLP) generally comprises the following several steps: firstly cutting off a single micro-chip from a wafer, and bonding the chip with the front surface facing downwards to an adhesive layer of a carrier by adopting a standard picking and placing device; then forming a plastic encapsulation layer and embedding the chip into the plastic encapsulation layer; and after the plastic encapsulation layer is solidified, removing the carrier and the adhesive layer, then performing a redistribution layer process and a reballing process; and finally performing cutting and testing. A redistribution layer (RDL) is an interface between a chip and a package in a flip chip module. A redistribution layer is an additional metal layer, consists of core metal top wiring and is used for outwards binding an I/O pad of a die to other positions such as a bump pad, etc. Bumps are usually arranged in a grid pattern, each bump is cast with two pads (one is located at the top and the other is located at the bottom), which are respectively connected with the redistribution layer and a package substrate. The traditional fan-out wafer level package easily causes an offset between the chip and the RDL, thereby resulting in low yield.
The package on package (POP) may allow a plurality of chips to be vertically stacked in a single package, vertically separated logic chip and memory chip ball arrays are integrated, stacked packages transmit signals through the standard IO interfaces, resulting in multiple folds of component density, and increased functions of a single package, therefore POP is widely applied to fields of mobile phones, personal digital assistants (PDA) and digital cameras, etc.
In advanced packaging, through-silicon via (TSV) technology has a great significance. It is a vertical electric connection technology for penetrating through a substrate (especially a silicon substrate). The TSV technology may replace nearly all wire bonding packaging and thus improve electrical performances of all types of chip packages, including integration level and chip size reduction, especially in advanced packaging such as system-in-package (SiP), wafer-level package (WLP) and 3D packaging. Fabrication of TSV includes fabrication of vias, deposition of insulating layers, filling of vias, and subsequent processes such as chemical mechanical planarization (CMP) process and redistribution (RDL) process, etc. The traditional POP is related to =TSV technology, there are a series of complex fabrication processes needed, consequently causing higher production costs and lower yield.
Therefore, it has become an important and urgent technical problem to be solved how to provide a fan-out package structure and a manufacturing method thereof to reduce the production cost and improve the yield.